FIG. 1 shows an illustrative configuration of a conventional PLL (Phase Locked Loop) circuit disclosed in Patent Publication 1. This conventional PLL circuit, shown in FIG. 1, includes a phase frequency detector (PFD) 11, a charge pump circuit (CP) 12, a low-pass filter (LPF) 13, a voltage-controlled oscillator (VCO) 14, and a divider circuit (DIV) 15. The phase frequency detector 11 compares the phase of rising of a reference clock signal (REFCLK) with that of a divided clock signal (DIVCLK), output from the divider circuit 15 and, if the divided clock signal lags or leads the reference clock signal, the phase frequency detector 11 outputs an up (UP) signal or a down (DN) signal, each being of a pulse width corresponding to the phase difference, respectively.
The charge pump circuit 12 receives UP and DN signals output from the phase frequency detector 11 and causes the current having a value corresponding to the pulse width of the UP signal to flow from a power supply to an output terminal thereof, thereby charging the output terminal, while causing the current having a value corresponding to the pulse width of the DN signal to flow from the output terminal to the ground, thereby discharging the output terminal. The charge pump circuit 12 outputs from the output terminal thereof an error signal corresponding to the phase/frequency difference detected by the phase frequency detector 11. The low-pass filter 13 receives the error signal output from the charge pump circuit 12 and generates a control voltage which is obtained by smoothing the error signal. The voltage-controlled oscillator 14 receives the control voltage output from the low-pass filter 13 and generates an output clock signal, the frequency of which is subjected to change to a higher value or to a lower value depending on a higher or lower value of the control voltage, respectively. The divider circuit 15 receives the output clock signal (VCOCLK) output from the voltage-controlled oscillator 14 and divides the output clock signal (VCOCLK) by a preset frequency division ratio to output the divided clock signal (DIVCLK). In this manner, the PLL circuit performs feedback control so that the reference clock signal (REFCLK) and the divided clock signal (DIVCLK) becomes coincident in phase and frequency with each other and hence the frequency of the output clock signal (VCOCLK) of the voltage-controlled oscillator 14 becomes a preset multiple of the frequency of the reference clock signal (REFCLK).
In unstable states, such as on power up, the oscillation frequency of the voltage-controlled oscillator 14 may become unusually high to exceed the limit of the toggle frequency of the divider circuit 15. In case the frequency of the output clock signal (VCOCLK) fed to the divider circuit 15 exceeds the maximum toggle frequency of the divider circuit 15, the divider circuit 15 continues to output a fixed level, as a result of which the phase frequency detector 11 continues to output the UP signal. This leads to a deadlock state in which the PLL circuit is unable to act as a negative feedback loop. In order to take a measure to meet the situation, the PLL circuit shown in FIG. 1 includes a deadlock detection circuit made up by a power-on reset circuit 25, a flip-flop 26, and an NMOS transistor 3. This deadlock detection circuit operates as follows:
First, until such time that the power supply voltage on power up reaches a preset value, an output signal of the power-on reset circuit 25 is activated to reset the divider circuit 15 as well as to set the flip-flop 26. An output of the flip-flop 26 turns the transistor 3 on to discharge an output of the low-pass filter 13.
Consequently, the voltage-controlled oscillator 14 oscillates at a low frequency without oscillating at an unusually high frequency. When the power supply voltage then reaches a preset value, an output signal of the power-on reset circuit 25 is inactivated to release the reset state of the divider circuit 15. The divider circuit 15 divides the frequency of the output of the voltage-controlled oscillator 14 to output the divided clock signal (DIVCLK). By the divided clock signal, the flip-flop 15 is reset to turn off the NMOS transistor 3. As from this time, the PLL circuit commences its normal operation.
[Patent Document 1]
JP Patent Kokai Publication No. JP-A-11-103249